1. Field of the Invention
The present invention relates to a memory circuit and, more particularly, to a memory that can have a block of address locations synchronously written to or read from in a burst fashion, with the address block bottom address stored in a mirror register, and a counter for incrementally writing to or reading from the memory block at an internally-derived address stored in a counter register and selected using a counter control signal.
2. Description of the Related Art
The following descriptions and examples are given as background only.
A typical mechanism in which to store data involves sending an address to that storage location in order to access that location, and reading from that addressable location, or writing to that addressable location. Accordingly, memory generally includes an address bus and a data bus, as well as control signals which control access thereof.
There are numerous forms of memory, such as mass storage devices or hard drives. Alternatively, memory can be embodied upon silicon or a single monolithic substrate, and such forms are known as semiconductor memory. Popular semiconductor memory includes random access memory (RAM), read only memory (ROM), and programmable read only memory (PROM), etc. Because each form of semiconductor memory operates differently from one another, the addressing of the memory locations and the data bus applicable to those locations, as well as the control signals, remain somewhat unique to one another.
As an example, RAM can be accessed in different ways. In many applications, related data are placed in contiguous locations within the RAM. In order to quickly access that data, a RAM can implement synchronous accessing whereby contiguous address spaces (or possibly non-contiguous spaces) can be accessed at sequential transitions of a clocking signal, rather than having to resort to independent accesses that require taking control of the external address bus. Such forms of memory are often referred to as synchronous memory, and a popular such memory is often labeled synchronous RAM.
If accesses can occur synchronously and if the target data is placed in a relatively contiguous space, then a natural benefit of synchronous memories is to perform a burst read or write operation. Essentially, a burst read or write (burst access) involves performing a load operation of a particular address, and then subsequently incrementing or decrementing a counter to point to the next addressable location until an entire block of addressable locations are accessed. Thus, a burst access involves externally reading a load address upon the external address bus, and then incrementing a counter placed internal to the memory, generally labeled “burst counter”. The only access on the external address bus is the initial load operation for the first memory location within the block being read. Thereafter, the counter simply increments or decrements to the next address space. Thus, the data from all address spaces within the block can be accessed by asserting the read/write operation and holding the particular (read or write) chip control signal active for as long as necessary to complete the burst access.
The term external address is generally recognized as the address bus that is external to the memory device or, more specifically, is the address bus coming from an execution unit (i.e., microprocessor) that, in response to an instruction, loads a particular address onto the external address bus that is then sent to the memory or the memory controller. Once the externally-loaded address is placed upon the external address bus and subsequently loaded unto the internal address bus, the memory or memory controller then performs the counter increment or decrement internal to the memory or memory controller. A benefit in performing a burst or block access is that the external address bus is only occupied for the first address. The counter, which might transition much faster than the external address, then takes care of the remaining addressable locations without having to thereafter involve the external address bus.
It may be desirable for the user to know the current memory address location at which the internal counter is pointing at a particular time, as well as the associated data at that address. Therefore, the concept of a read-back occurs whenever the user might implement an instruction through a control signal external to the memory controller or memory device. That instruction can be fed from an external pin or decoded from multiple pins into the memory device, which then instructs the counter to send back the particular address to which it is pointed and/or the data so that the user can then read that correspondence. Examples of an external-derived read-back mechanism in which the counter pointed-to address and data is read back is set forth in, for example, U.S. Pat. Nos. 6,789,180 and 6,782,147.
While there is benefit in knowing where the counter is within the block of data, and reading back the address and corresponding data values, there is even more value in being able to control the counter and the address and/or corresponding data values pointed to by that counter. Therefore, it would be desirable to implement a system which can not only read back the internally-derived (counter value) address and corresponding data, but also generate an address via the count value entirely internal to the memory controller or memory device. By beneficially controlling the count value and, thus, the corresponding address and data values to which that pointer is directed, it would be of even further value to do so without involving or occupying the external address bus.
Therefore, the desired system achieves the stated benefit of being able to derive an address location from among any memory addressable location solely internal to the memory controller or semiconductor memory device without having to take control of, manipulate, or in any way access or place an address upon an external address bus coupled between an execution unit and the memory controller or memory device. This frees up bandwidth on the external address bus and also allows for quicker memory address generation since such generation occurs solely internal to the controller or device without having to contend with or keep track of the pipelined addressing mechanisms normally associated with conventional memories that have priority control signals and coding on the external control signal bus.